Develop and integrate foundry rule decks & technology files to support PDKs. Responsible for physical verification methodology and QA of integrated PDKs. Support layout teams in verification flow issues and develop automation framework for efficiency improvement.

Principal Design Engineer at Cadence with expertise in high-speed Serdes, I/O Design, and mentoring junior engineers. Requires experience in cutting-edge technology nodes and strong communication skills.

Cadence is seeking a highly motivated Memory Design Engineer with 8-11 years of experience to join their team in Hyderabad. Responsibilities include circuit design, simulation, verification, and silicon bring-up for memory design blocks. The ideal candidate should have a strong technical background in memory designs and tools like Cadence, Mentor Graphics, and Synopsys.