Top Design Engineer Jobs in Hyderabad

Perform block- and subsystem-level ASIC physical implementation from netlist to GDS: floorplanning, placement, CTS, routing, timing closure, power and PPA optimization, physical verification, ECOs, signoff, and automation via Tcl/Python while collaborating with RTL/DFT/DV teams.

Lead and execute ASIC backend implementation from RTL handoff through tapeout. Own floorplanning, power/plaus, placement, CTS, routing, timing closure, ECOs, and signoff. Define physical verification/signoff methodology, debug complex signoff issues, drive automation and shift-left practices, and coordinate contractors, vendors, and cross-functional teams to meet tapeout quality.

Lead hardware product innovation for greenhouses and related systems: conduct farmer discovery, ideate and prototype, validate designs in R&D and field, test structural loads, create SOPs and QA/QC documentation, and manage projects and stakeholders to deliver scalable, farmer-centric solutions.

Design and validate RF subsystems for large parabolic and earth station antennas, perform RF simulations and link budget analysis, integrate LNAs/BUCs/waveguides/filters/amplifiers, support testing, calibration, and environmental validation, and produce technical documentation while collaborating with mechanical, systems, baseband, and control teams.

Design high-performance analog-to-digital and digital-to-analog converters, evaluate silicon, and oversee layout in advanced CMOS processes.

The Senior Analog IC Design Engineer will work on high-speed analog designs, collaborate with teams for implementation, and analyze performance tradeoffs.

Design and verify high-performance digital and mixed-signal ICs, focusing on RTL design, behavioral modeling, and digital control circuits.

The Senior Digital Design Engineer will design, verify, and validate digital architecture for automotive and space applications, focusing on RTL and FPGA.

The role involves high-performance analog and mixed-signal IC design, from specification to product introduction, requiring extensive experience in circuit design and lab evaluation.

Own end-to-end UI/UX and frontend implementation: design user flows, craft high-fidelity prototypes, build responsive React+TypeScript interfaces, implement scalable component architecture, integrate with REST/GraphQL APIs, optimize performance, and collaborate with backend and product teams in a regulated life-sciences context.

Build production-quality, pixel-accurate UI components and interactions in React Native; prototype in Figma with designers; own the design system and component library; improve performance, animations, and cross-platform UI architecture; define design-to-dev tooling and collaborate across design and engineering.

The Physical Design Engineer will implement AI acceleration SoCs, focusing on RTL-to-GDSII flows, synthesis, timing analysis, and collaboration with internal and external teams.

The Staff ASIC Design Engineer will lead ASIC design projects, implement micro-architecture optimizations, and collaborate across teams to develop silicon products.

Develop and implement SoCs, focusing on micro-architecture design, RTL coding, synthesis, and timing closure, while collaborating with various teams throughout ASIC development.

The ASIC Design Engineer will design and implement SoCs, optimize performance, collaborate with teams, and support chip validation through the design flow.

The Design Engineer role focuses on digital design using firmware and Verilog/System Verilog for candidates with disabilities. No specific salary is indicated.

Design, develop and integrate building management and controls for modular datacenter MEP systems. Own control architecture, PLC/HMI/SCADA programming, protocols, vendor review, FAT/SAT commissioning, troubleshooting, and mentor junior controls engineers while aligning with cybersecurity and IT requirements.

Design and verify ASIC hardware, optimize designs for power and performance, collaborate on architectural decisions, and support integration activities.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Lead full-chip or large-block physical implementation from netlist to GDSII. Drive floorplanning, placement, CTS, routing, STA timing closure, DRC/LVS/EM/IR signoff, ECOs, hard-macro integration, PPA optimization, and automation scripting while collaborating with RTL, architecture, verification, and foundry teams.

As a Demo Engineer, you support pre-sales by designing AI-driven demos and proof of concepts, collaborating closely with teams to showcase Cresta's capabilities.

As a Design Verification Engineer, you will verify AI hardware components, develop verification infrastructure, and automate testbench processes primarily using SystemVerilog/UVM.

Design and engineer grid-tied solar PV systems (1 kW–5 MW) and small-scale BESS. Create conceptual layouts, single-line diagrams and electrical schematics. Support project development, execution, and provide technical sales support and client-facing explanations of system feasibility and performance.

Lead development, optimization, and verification of digital silicon IP from model to bring-up. Create and maintain specs, block diagrams, and documentation. Characterize IP performance using industry-standard tools and flows, including FPGA simulation and emulation. Collaborate with architecture, physical design, and software teams and lead verification engineers.

Design and implement RTL and microarchitectural components for SoC/IP using SystemVerilog/Verilog. Optimize PPA, collaborate with verification and physical design teams, support integration, timing closure, simulation, GLS, and silicon bring-up, and contribute to design documentation and reviews.