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Design-for-Test Engineering role at NVIDIA involving crafting creative solutions for DFT architecture, verification, and post-silicon validation on complex semiconductor chips. Responsibilities include design and implementation of state-of-the-art test access mechanisms, memory BIST, and scan compression.

As an ASIC Verification Engineer at NVIDIA, you will be responsible for building verification test benches and methodologies to verify DFT features in complex IP's/Sub-systems/SOC's. You will collaborate with multi-functional teams and strive to improve the quality of DFT methods. Ideal candidates have a BSEE or MSEE with experience in DFT verification, expertise in System Verilog, UVM/VMM, and strong programming skills in C++, Perl, Python, or Tcl.