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Hardware • Software • Semiconductor
The Staff Engineer will lead AMS verification for mixed-signal SoCs, developing models and tests while collaborating across teams to ensure design performance and functionality.
Top Skills:
Ams Simulation ToolsCadenceMentor ToolsPerlPythonSynopsysSystemverilogTclVerilogVerilogams
Artificial Intelligence • Hardware • Information Technology • Machine Learning • Semiconductor
The Staff Engineer will focus on memory circuit design verification, including circuit simulations, debugging failures, and ensuring accurate SDF annotation coverage using advanced memory techniques.
Top Skills:
Dc AnalysisGate Level SimulationHbm Memory VerificationSdf AnnotationSpice SimulationStatic Timing AnalysisSystem VerilogTransient AnalysisUvmVerilog
3D Printing
Responsible for physical verification of SOCs and blocks, addressing design challenges and ensuring compliance with DRC, LVS, ERC, and other standards.
Top Skills:
DfmDrcErcEsdGds2LvsOpc
Responsibilities:
- Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS).
- Run digital/mixed-signal simulations as well as formal verification.
- Work closely with the design team to create a verification strategy and detailed verification plan.
- Develop tests, run regressions and monitor coverage to ensure tape-out quality.
- Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.
- Support post-silicon bring-up and debug, for bench validation and automated test equipment (ATE) testing.
- Improve verification scalability and portability from project to project by environment enhancement and tools automation.
Minimum Qualifications:
- 3+ years experience in the semiconductor industry
- M.S. in EE/CS/CE or higher
- Hands-on experience with SystemVerilog as High-level Verification Language and UVM implementation.
- Debugging digital simulation in RTL and gate-level netlist isolates issues in both module and system levels.
- Scripting experience in Python or Perl.
- Clear understanding of ASIC design flow
- Solid analytical and problem-solving skills
- Independent, self-motivated, rigorous, team player and able to follow through
- Excellent verbal and written communication skills
Preferred:
- Experience of setting up UVM verification environment from scratch
- Familiarity with VHDL or System Verilog RNM
- Automation of verification flow with Python/Perl in an industrial setting
- Analog behavioral model development/verification experience
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