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NXP Semiconductors

Sr. Lead ASIC design Engineer - Digital Design

Reposted 14 Days Ago
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In-Office
Hyderabad, Telangana, IND
Senior level
In-Office
Hyderabad, Telangana, IND
Senior level
Define hardware architectures for AI inference SoCs, oversee design from specification to debug, and collaborate with various teams for performance analysis and validation.
The summary above was generated by AI
  • Key Responsibilities
  • Define and implement hardware architectures optimized for AI inference SOC's
  • Contribute to micro-architecture definition and evaluate design trade-offs for complex SOC including custom-ISA based processors, high-speed interconnects & high-bandwidth IO's
  • Own features end-to-end: specification → RTL → integration → synthesis → debug
  • Collaborate with physical design teams on synthesis, timing closure, and power optimization.
  • Collaborate with verification team to ensure design correctness.
  • Work with architect engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.
  • Required Qualifications
  • 7+ years of experience in ASIC/SoC RTL design
  • Strong Verilog/SystemVerilog coding skills
  • Solid understanding of synthesis, timing, and power analysis
  • Experience with Lint/CDC/RDC flows
  • Strong debugging and root-cause analysis capability

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NXP Semiconductors Gachibowli, Telangana, IND Office

1st Floor, Block 3 , DLF Cyber City Plot # 129-132, APHB Colony, Gachibowli, Telangana, India, 500019

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