The Senior Verification Engineer will define verification architecture, implement methodologies, develop test plans, analyze simulation failures, and generate reports.
The Verification Engineer will define verification architecture, implement verification environment for block level, SoC subsystems and SOC top level design that use advance verification methodologies and meet established content, performance, quality, cost and schedule goals. He/She will also be responsible for the simulations of the SOC
Responsibilities
- Define overall verification strategies, methodologies, and simulation environment
- Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.
- Develop, maintain and publish verification specifications.
- Analyze and debug simulation failures
- Generates code coverage and functional coverage report
- Run gate level simulation and debug them.
- Perform the constraint assertion-based verification
Qualifications and Skills
- BS in EE with 3+ years of experience or MS in EE with 1+ year experience
- Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
- Fluent in verification language such as UVM/OVM/System Verilog, Vera, Verilog
- Experience in writing Test-plans and creating directed and random test cases
- Strong scripting skills in Perl, Python, Linux shells etc.
Top Skills
Asic Simulation Tool
Linux Shells
Ovm
Perl
Python
System Verilog
Uvm
Vera
Verification Language
Verilog
Similar Jobs
3D Printing
The SoC Verification Engineer will create test plans, perform various verification tasks, collaborate with R&D teams, and ensure quality sign-offs for SoC products.
Top Skills:
C/C++Eda ToolkitsPerlPythonShellSystem VerilogTclUvm MethodologyVerilog
.jpeg)
Artificial Intelligence • Hardware • Information Technology • Machine Learning
The role involves defining verification strategy for RTL, developing and maintaining verification testbenches, debugging, and communicating verification status to stakeholders.
Top Skills:
PerlPythonRtlSimvisionSv-UvmVerdiVerisiumVirtuosoXcellium
Artificial Intelligence • Hardware • Information Technology • Machine Learning
The role involves developing advanced verification components for SOC designs, executing verification plans, debugging issues, and ensuring quality delivery. Requires expertise in NAND, DDR, and PCIe verification with experience in UVM-based test-benches.
Top Skills:
AsicDdrNandPcieSimulation ToolsSystem VerilogUvm
What you need to know about the Hyderabad Tech Scene
Because of its proximity to leading research institutions and a government committed to the city's growth, Hyderabad's tech scene is booming. With plans to establish India's first "AI city," the city is on track to become one of the world's most anticipated tech hubs, with companies like TransUnion, Schrödinger and Freshworks, among others, already calling the city home.
