Senior Staff ASIC Design Engineer

Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure—from data centers to next generation cloud and AI platforms—by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems. 

Founded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award. 

At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world. 

If you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey. 

• Help develop the design and implementation/ integration of SoCs.
• Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks
• Support prototyping, test program development, chip validation, and chip life until production maturity.
• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

• 12+ years of experience in RTL logic design, verification, synthesis, and timing optimization;
• Proficient in writing clear, implementable micro-architecture specifications;
• Expertise in writing efficient RTL code in Verilog and SoC integration
• Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure;
• Should have worked on interface protocols like PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI, etc.
• Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce.
• Fluency with scripting languages (e.g., Perl, Python);
• Must have gone through at least one complete tape-out cycle.
• Preferred: Silicon bring-up and debug experience
• Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA.

Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.