Define and own architecture for AI inference chip; collaborate with RTL designers and software teams; lead PPA analysis and maintain performance models.
Architecture & Micro-Architecture
- Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.
- Collaborate with software to co-optimize hardware features for AI workloads.
- Collaborate with RTL designers to identify and complex technical issues/risks. Review and guide RTL implementation, ensuring consistency with architectural intent and timing/power goals
- Collaborate with Physical-design teams for Area/Floorplan refinment, Timing targets etc.
- Define and document interface specifications, control/status logic, and pipeline structures.
- Lead PPA analysis and trade-off discussions across RTL and architecture.
Modelling & Analysis
- Develop and maintain high-level architecture and performance models.
- Use simulation and architectural models to guide RTL-level improvements.
More information about NXP in India...
#LI-2734Top Skills
Ai Inference Chip
High-Speed Interface Subsystems
Performance Models
Rtl Design
Simulation
NXP Semiconductors Gachibowli, Telangana, IND Office
1st Floor, Block 3 , DLF Cyber City Plot # 129-132, APHB Colony, Gachibowli, Telangana, India, 500019
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