The Principal Design Engineer at Cadence will develop test plans and verification infrastructure for complex IPs and SoCs, create verification environments using UVM methodology, and drive verification closure. The role requires collaboration with architects and designers to ensure functional correctness and coverage, alongside the management of test bench creation and execution for various protocols.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
Job responsibilities:
BE/BTECH/ME/MTECH Or Equivalent Degree
RESPONSIBILITIES:
- Develop test plans, tests , and verification infrastructure for complex IP’s/sub-system/SOC’s.
- Create verification environment using UVM methodology.
- Create reusable bus functional models, monitors, checkers, and scoreboards.
- Drive functional coverage driven verification closure.
- Work with architects, designers and DFT teams.
SKILL SETS:
- BTech/ MTech with 10-14 years of experience.
- IP/Sub-system/SOC level verification experience.
- Expert in developing test bench/test case using System Verilog & UVM.
- Experience in leading verification closure of complex IP/SOC for at least one project.
- Experience with code coverage, functional coverage & assertions is desired.
- Experience in at least one of the following areas:
- CPU verification
- Memory controller verification
- DDR Protocol - DDR4, DDR5, LPDDR4 and LPDDR5
- USB 2 and USB 3 protocol
- PCIE
- Bus protocols (AXI/AHB/APB)
- Exposure to industry standard verification tools for simulation and debug
- Good debugging and problem-solving skills.
- Good communication skills
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