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RESPONSIBILITIES:
Should be able to develop test plans, tests , and verification infrastructure for complex IP’s/sub-system/SOC’s.
Should be able to create verification environment using UVM methodology or any equivalent methodology.
Create reusable bus functional models, monitors, checkers, and scoreboards.
Should have experience in functional coverage driven verification closure.
SKILL SETS:
- BTech/ MTech in Engineering
- 10-12 years of VLSI industry experience in Verification.
- Strong experience in SoC level verification. Knowhow of IP/Subsystem experience
- Good experience in developing test bench/testbench components, testplans, test cases; developing functional coverage, assertions; coverage analysis.
- Strong in UVM, SV
- Knowledge of protocols like UCIe, PCIe, DDR, USB, AMBA protocols preferred
- Strong individual contributor and a mentor with sound debug and problem solving skills
- Strong working-level experience of verification cycle for complex SOCs
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