Physical Silicon Design Engineer (India)

Introduction

Edgecortix Inc. is seeking a Hardware Design Engineer with proven RTL/logic and ASIC design expertise. If you have strong desire to build state-of-the-art digital chips and systems join us and let's reshape the future of AI.

Your Role and Responsibilities:

Ideal candidates will have expertise in several of the following areas:

• Work on physical implementation of SoCs, chiplets and block hardening for Edgecortix AI acceleration products in house as well as provide guidance to external design partners.
• Implement and improve in house physical implementation flows.
• Commit library and cell studies, evaluate libraries from different vendors and determine beneficial implementation strategies.
• Constantly look for ways to optimize PPA of the product at all different levels (logic and architecture, synthesis and P&R flows, floorplan, libraries, technology selection)
• Run synthesis, P&R, CTS flows using industry standard tools from Synopsys and Cadence.
• Perform power grid generation and IR-drop analysis.
• Own power analysis activities to ensure design is within the budget, and keep track of design PPA for continuous improvement.
• Work with the design team to create constraints and power intent.
• Work in a tight loop with the architecture and RTL design team providing continuous feedback to architecture and logic implementation. Analyze limiting factors and driving improvements.
• Participate in new architecture conceptualization, doing early stage analysis experiments and projections of various decision outcomes. Participate in power and area budgeting and scoping activities.
• Perform STA to ensure design meets timing across multiple corners and scenarios.
• Analyze timing failures and work with the design team to resolve the root cause of the issue.
• Create floor plans and come up with best ways to partition architecture for hierarchical implementation.
• Create ECO patches based on design team inputs.
• Stay in touch with the industry trends and drive new tools, latest techniques and methodologies adoption internally.

Required Qualifications:

• Bachelor in Electrical Engineering, Computer Engineering, Computer Science or similar.
• 5+ years of hands-on experience with physical design of high-performance or power-efficient SoC designs. Prior experience in tape out of complex SoC`s involving multiple IP`s (PCIE,DDR, CPU`s etc.)
• Good understanding of the end-to-end RTL to GDSII flow.
• Strong understanding of physical design decisions on power efficiency and performance.
• Hands on experience across synthesis, P&R, CTS and timing closure.
• Hands-on experience of doing STA using industry standard tools such as Cadence Tempus.
• Hands-on experience with advanced technology nodes such as 16/12 nm and below.

Preferred Qualifications:

• Master in Electrical Engineering, Computer Engineering, Computer Science or similar.
• 10+ years of hands-on experience with physical design of high-performance or power-efficient SoC designs. Chiplet implementation and sign-off experience is a plus.
• Understanding and ability to optimize interrelations between physical design of the die and package design.
• Hands on experience of doing and optimizing across P&R, floor plan, clock tree synthesis and power grid generation.
• Hands on experience in IR-drop analysis , LVS , electrical verification such as electrical rule checks, shorts, ESD checks, etc.
• Hands on experience with low-power, multi voltage, multi power domain designs, power gating, isolation, ability to define and maintain UPF based on design team requirements,
• Good grasp of timing closure methodologies. Experience of closing complex multi-corner multi-scenario designs.
• Deep understanding of physical factors contributing to design performance such as noise, crosstalk, and OCV effects etc.
• Hands on experience in ECO implementation, creating and applying ECO patches based on RTL design team changes.
• Outstanding analytical and communication skills, an ability to communicate with the RTL design team to achieve globally optimal design outcomes. Experience in providing actionable feedback for logic optimization.
• Strong ability to drive issues to resolution across different counterparties such as RTL design team, package design team and tool and IP vendors.

What’s in it for you?

Make a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.

Location

Hyderabad is the primary work location, but Bangalore is also available.

And Hybrid Remote working is allowed.

Benefits and Perks

• Highly competitive salary and stock options
• Flex work time
• Top-tier employee benefits