We are hiring a Physical Design Engineer to join our VLSI backend team. You will work on floorplanning, placement, and routing for design blocks, contributing to timing and area closure from RTL handoff through tapeout.
Key Responsibilities:
- Floorplanning, power planning, placement, and clock tree synthesis
- Routing, DRC/LVS clean-up, and signoff checks
- Timing closure at block level across corners and modes
- Physical verification and ECO implementation
- Collaborate with STA, DFT, and RTL design teams on block-level closure
- Support full-chip integration activities as needed
Requirements:
- 4-5 years of hands-on experience in physical design (floorplan through signoff)
- Proficiency with industry-standard P&R tools (ICC2/Innovus or equivalent)
- Solid understanding of STA fundamentals and DRC/LVS signoff flows
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