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Cadence Design Systems

Lead Design Engineer

Job Posted 11 Days Ago Posted 11 Days Ago
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Hyderabad, Telangana
Mid level
Hyderabad, Telangana
Mid level
The Lead Design Engineer at Cadence is responsible for AMS verification, developing test plans, and debugging issues. Candidates should have expertise in Verilog and a moderate understanding of analog design and SERDES protocols. The role involves collaborating within a team to deliver innovative electronic design solutions.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day

AMS Verification( 4-15yrs of exp)

Location: Hyderabad

BE/BTECH/ME/METCH or Equivalent Degree

  • From Verilog coding
    • Proficient in Verilog coding
    • Verilog problem solving and BMOD coding.
  • From the  analog design understanding
    • Analog design moderate understanding
      • Should be able to know SERDES/ DDR Phy lane level functionality and need of blocks like VREG, DELAY, RX/TX
  • AMS Verification Co-Sim Setup, Methodologies and tradeoffs
  • Architectures knowledge on SERDES protocols
  • Understanding of Verification Environment
  • Test Plan developments
  • Debug Skills and issues communications

We’re doing work that matters. Help us solve what others can’t.

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