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Cadence Design Systems

Design Engineer 2

Posted 19 Hours Ago
Be an Early Applicant
Hyderabad, Telangana
Mid level
Hyderabad, Telangana
Mid level
The Design Engineer 2 position at Cadence involves conducting verification in the VLSI industry, particularly at the SOC level. Responsibilities include developing test benches, creating test plans and cases, conducting coverage analysis, and debugging. A strong knowledge of SystemVerilog and UVM is essential, along with problem-solving skills and participation in the entire verification cycle.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Requirement:

• BTech/ MTech in Engineering
• 4-5 years of VLSI industry experience in Verification.
• SOC level verification experience preferred
• IP or Subsystem or SOC level verification experience
• Strong knowledge of SV & UVM
• Experience in developing test bench/testbench components, testplans, test cases; developing functional coverage, assertions; coverage analysis. Gate level verification experience would help
• Strong individual contributor with good debug, problem solving skills
• Good knowhow of overall verification cycle

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Sv
Uvm

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